In some electronic systems or devices, it is desirable to synchronize a clock signal to some defined standard or an external repetitive event. However, generating such a clock signal can present challenges when the target frequency is very high with respect to the synchronizing event, and the clock must be exact (i.e., relatively low jitter) and fast responding with respect to the synchronizing event.
One particular environment where such clock requirements can be important is a system having data conversion circuits that operate at a relatively high frequency with respect to a rate at which data is received. As but one very particular example, audio data may be received at an interface (e.g., serial interface) associated with a relatively low frequency signal be converted into analog audio signals by digital-to-analog converters (DACs) operating at a sampling rate that is tens of thousands of times faster than the low frequency signal. For sufficient performance, a clock signal must not only meet the sampling rate, but it must also be rigorously locked (e.g., low jitter) to the lower frequency signal. Further, the clock synthesis approach should be capable of rapidly responding to changes in the lower frequency signal.
Clock multiplication using one or more phased lock loops (PLLs) is known. However, achieving very large multiplication factors with a single PLL may suffer from unacceptably high amounts of phase noise. Higher phase precision may be achieved by employing multiple PLLs. However, such solutions may undesirably increase response time, and may be more expensive to implement when realized with a single integrated circuit device.